Yield and Cost Analysis of a Reliable NoC

The yield and cost of a multi-core chip improve significantly through the addition of some spare cores in the system. In this paper, we model the manufacturing and service cost of an NoC with spare wires and routers as well as spare cores. We apply our analysis on an exemplary 9-core processor and o...

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Hauptverfasser:	Shamshiri, S., Kwang-Ting Cheng
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	burn-in elimination cost optimization Costs distributed redundancy Field programmable gate arrays Logic devices Manufacturing processes Multicore processing Network-on-a-chip NoC Programmable logic arrays Redundancy SoC spare-enhanced resiliency Virtual manufacturing Wires yield analysis
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Beschreibung
Zusammenfassung:	The yield and cost of a multi-core chip improve significantly through the addition of some spare cores in the system. In this paper, we model the manufacturing and service cost of an NoC with spare wires and routers as well as spare cores. We apply our analysis on an exemplary 9-core processor and on an Intel 80-core processor, and show that a spare scheme can significantly improve the reliability, reduce the cost, and substitute for the burn-in process.
ISSN:	1093-0167 2375-1053
DOI:	10.1109/VTS.2009.34