A single chip HDD PRML channel

A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 /spl mu/m BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/s...

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Bibliographische Detailangaben
Hauptverfasser:	Ahn, T.W., Chen, G., Hua, B., Kim, C.J., Knee, D., Kondo, A., Kuo, B., Lan, I.J., Ng, M., Shen, F., Yeh, N.H., Young, J.K.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	BiCMOS integrated circuits Cutoff frequency Delay lines Finite impulse response filter Gain control Hard disks Magnetic recording Maximum likelihood decoding Maximum likelihood detection Viterbi algorithm
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Beschreibung
Zusammenfassung:	A PRML (Partial Response Maximum Likelihood) channel chip employing a mixed-signal 0.8 /spl mu/m BiCMOS process for hard disk drive (HDD) applications is described. This chip performs the complete write, read, and servo functions using only five external components with a data rate of up to 120 Mb/sec. Under normal operating conditions the power dissipation is less than 800 mW. The on-chip circuitry includes ADC, VGA, FIR filter, Viterbi decoder, two PLL's, etc.
DOI:	10.1109/CICC.1996.510560