A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs

A 60pJ, 3-Clock Rising Time, VTH Loss Compensated Word-Line Booster Circuit for 0.5V Power Supply Embedded/Discrete DRAMs

A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.

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Bibliographische Detailangaben
Hauptverfasser: Tanakamaru, S., Takeuchi, K.
Format: Tagungsbericht
Sprache:eng ; jpn
Schlagworte:
Capacitors
Charge pumps
Circuits
Clocks
Energy consumption
Logic
Parasitic capacitance
Power supplies
Random access memory
Voltage
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Beschreibung
Zusammenfassung:A low power high-speed word-line booster is proposed for 0.5 V operation embedded and discrete DRAMs. Compared with the conventional boosters, the rising time and the power consumption are 25% and 48%, respectively, with the same circuit area.
ISSN:2159-483X
DOI:10.1109/IMW.2009.5090572