A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

A multiplier-accumulator macro for a 45 MIPS embedded RISC processor

This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication fo...

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Veröffentlicht in:IEEE journal of solid-state circuits 1996-07, Vol.31 (7), p.1067-1071
Hauptverfasser: Murakami, H., Yano, N., Ootaguro, Y., Sugeno, Y., Ueno, M., Muroya, Y., Aramaki, T.
Format: Artikel
Sprache:eng
Schlagworte:
Algorithm design and analysis
CMOS technology
Costs
Delay
Engines
Flip-flops
Information systems
Microelectronics
Reduced instruction set computing
Throughput
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Zusammenfassung:This paper describes a high speed and area effective multiplier-accumulator for an embedded RISC processor. The point of architecture is to utilize a full adder array and the Booth's encoder twice in a cycle. The multiplier-accumulator executes one multiply-add operation (32 b multiplication followed by 64 b addition) per cycle at 56.5 MHz. The area is 2.35 mm/sup 2/ with 0.4 /spl mu/m CMOS technology.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.508224