ROS: an extremely high density mask ROM technology based on vertical transistor cells

A novel mask-ROM technology enabling a twofold packing density compared to conventional, planar ROM layout relying on the same design rules is presented. The key of the new technology is a cell concept based on a vertical MOS transistor in a trench, and a doubling of the bitline pitch by use of the trench bottom as additional bitline. The features of the ROS-technology are demonstrated by means of a 1 Mbit demonstrator memory. Since vertical transistors are manufacturable far below channel lengths of 100 nm, the technology is very promising for mass storage and thus for the replacement of conventional mass storage devices by semiconductor-memories.