A neuron MOS transistor-based multiplier cell

A neuron MOS transistor-based multiplier cell

Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic ap...

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Bibliographische Detailangaben
Hauptverfasser: Weber, W., Prange, S.J., Thewes, R., Wohlrab, E.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Capacitance
CMOS logic circuits
Coupling circuits
Dielectrics
Equations
Logic devices
MOSFETs
Neurons
Nonvolatile memory
Pulse inverters
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Beschreibung
Zusammenfassung:Based on the neuron MOS transistor principle a multiplier circuit is designed for the first time. High-speed measurements are presented that qualify the principle of threshold logic for a new design principle. This represents a major breakthrough of packing density improvement of CMOS-based logic applications.
ISSN:0163-1918
2156-017X
DOI:10.1109/IEDM.1995.499282