Scaling-down of cone-like field emitter using LOCOS

As an attempt to develop a field emitter array (FEA) with sub-half-micron gate openings for low voltage operation, a new fabrication method has been proposed and demonstrated. The key element of the new process is forming the gate insulator by local oxidation of silicon (LOCOS), resulting in the reduction of the gate hole size due to the lateral encroachment of oxide, ultimately, comparable with the nitride disc size formed by a conventional contact printer. Feasibility of scaling down the gate hole size of a field emitter to sub-half-micron has been proven successfully. For a 2500-tip array with 450-nm-diameter gate openings, the anode current of 115 /spl mu/A (/spl sim/50 nA/tip) was measured at the gate voltage of 41 V, while the gate current was less than 0.3% of the anode current. Simulation results, which were compared with the measured emission characteristics, indicate that the lowered operating voltage of the scaled field emitter is caused by field enhancement not only due to the reduction of gate hole size but also due to that of the tip radius.