Dynamic frequency-switching clock system on a quad-core Itanium® processor
The700mm 2 65nm Itanium reg processor codenamed Tukwila integrates four cores and a system interface with six QuickPath reg interconnect channels and four memory interconnect channels. The large die and high level of integration coupled with process variability present clock-system design challenges...
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| creator | Allen, A. Desai, J. Verdico, F. Anderson, F. Mulvihill, D. Krueger, D. |
| description | The700mm 2 65nm Itanium reg processor codenamed Tukwila integrates four cores and a system interface with six QuickPath reg interconnect channels and four memory interconnect channels. The large die and high level of integration coupled with process variability present clock-system design challenges in the areas of power consumption and variability compensation that discuss in this paper. The clock system, which is a cascaded-PLL architecture with an initial filter PLL that receives a 133 MHz reference clock. This maiden PLL filters reference-clock jitter and outputs a 133 MHz clock to 13 downstream PLLs. Each downstream PLL has a duty-cycle corrector that monitors and corrects the end-of-route duty cycle. |
| doi_str_mv | 10.1109/ISSCC.2009.4977308 |
| format | Conference Proceeding |
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| identifier | ISSN: 0193-6530 |
| ispartof | 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.62-63,63a |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_4977308 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay Electrodes Frequency Integrated circuit interconnections Mobile handsets Random access memory Read-write memory Routing Switches |
| title | Dynamic frequency-switching clock system on a quad-core Itanium® processor |
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