A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications
The NAND flash memory was originally designed to target solid-state mass storage applications. Key requirements of mass storage, low cost and high serial access throughput, have been achieved by sacrificing a non-critical feature, fast random access. For a quantum step in cost reduction, the multi-l...
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| creator | Tae-Sung Jung Young-Joon Choi Kang-Deog Suh Byung-Hoon Suh Jin-Ki Kim Young-Ho Lim Yong-Nam Koh Jong-Wook Park Ki-Jong Lee Jung-Hoon Park Kee-Tae Park Jang-Rae Kim Jeong-Hyong Lee Hyung-Kyu Lim |
| description | The NAND flash memory was originally designed to target solid-state mass storage applications. Key requirements of mass storage, low cost and high serial access throughput, have been achieved by sacrificing a non-critical feature, fast random access. For a quantum step in cost reduction, the multi-level cell is combined with NAND flash memory. This 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control and is made practical by significantly reducing program disturbs. |
| doi_str_mv | 10.1109/ISSCC.1996.488501 |
| format | Conference Proceeding |
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This 128 Mb multi-level NAND flash memory stores two bits per cell by tight programmed cell threshold voltage (Vth) control and is made practical by significantly reducing program disturbs.</description><subject>Circuit noise</subject><subject>Circuit simulation</subject><subject>Costs</subject><subject>Flash memory</subject><subject>Latches</subject><subject>Pins</subject><subject>Solid state circuit design</subject><subject>Threshold voltage</subject><subject>Throughput</subject><subject>Voltage control</subject><issn>0193-6530</issn><issn>2376-8606</issn><isbn>9780780331365</isbn><isbn>0780331362</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1996</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNp9jsFqAjEUAB-tha7VD2hP7wd2--JzY3KUtaIFvVi8SpRsm5J0l2Qr-PcKehYG5jCXAXgVVAhB-n252VRVIbSWxVipksQDZCOeyFxJko8w1BNFF5gFy7IHGQnNuSyZnqGf0i8RlVqqDD6nyAXjFsVI4WqP4d93Lvf2aD2up-sZ1t6kHww2NPGEdRMxmJQwdU003xZN23p3MJ1r_tIAnmrjkx3e_AJv84-vapE7a-2ujS6YeNpdb_luPAPNFD16</recordid><startdate>1996</startdate><enddate>1996</enddate><creator>Tae-Sung Jung</creator><creator>Young-Joon Choi</creator><creator>Kang-Deog Suh</creator><creator>Byung-Hoon Suh</creator><creator>Jin-Ki Kim</creator><creator>Young-Ho Lim</creator><creator>Yong-Nam Koh</creator><creator>Jong-Wook Park</creator><creator>Ki-Jong Lee</creator><creator>Jung-Hoon Park</creator><creator>Kee-Tae Park</creator><creator>Jang-Rae Kim</creator><creator>Jeong-Hyong Lee</creator><creator>Hyung-Kyu Lim</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>1996</creationdate><title>A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications</title><author>Tae-Sung Jung ; Young-Joon Choi ; Kang-Deog Suh ; Byung-Hoon Suh ; Jin-Ki Kim ; Young-Ho Lim ; Yong-Nam Koh ; Jong-Wook Park ; Ki-Jong Lee ; Jung-Hoon Park ; Kee-Tae Park ; Jang-Rae Kim ; Jeong-Hyong Lee ; Hyung-Kyu Lim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-ieee_primary_4885013</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1996</creationdate><topic>Circuit noise</topic><topic>Circuit simulation</topic><topic>Costs</topic><topic>Flash memory</topic><topic>Latches</topic><topic>Pins</topic><topic>Solid state circuit design</topic><topic>Threshold voltage</topic><topic>Throughput</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Tae-Sung Jung</creatorcontrib><creatorcontrib>Young-Joon Choi</creatorcontrib><creatorcontrib>Kang-Deog Suh</creatorcontrib><creatorcontrib>Byung-Hoon Suh</creatorcontrib><creatorcontrib>Jin-Ki Kim</creatorcontrib><creatorcontrib>Young-Ho Lim</creatorcontrib><creatorcontrib>Yong-Nam Koh</creatorcontrib><creatorcontrib>Jong-Wook Park</creatorcontrib><creatorcontrib>Ki-Jong Lee</creatorcontrib><creatorcontrib>Jung-Hoon Park</creatorcontrib><creatorcontrib>Kee-Tae Park</creatorcontrib><creatorcontrib>Jang-Rae Kim</creatorcontrib><creatorcontrib>Jeong-Hyong Lee</creatorcontrib><creatorcontrib>Hyung-Kyu Lim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Tae-Sung Jung</au><au>Young-Joon Choi</au><au>Kang-Deog Suh</au><au>Byung-Hoon Suh</au><au>Jin-Ki Kim</au><au>Young-Ho Lim</au><au>Yong-Nam Koh</au><au>Jong-Wook Park</au><au>Ki-Jong Lee</au><au>Jung-Hoon Park</au><au>Kee-Tae Park</au><au>Jang-Rae Kim</au><au>Jeong-Hyong Lee</au><au>Hyung-Kyu Lim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications</atitle><btitle>1996 IEEE International Solid-State Circuits Conference. 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| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0193-6530 |
| ispartof | 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC, 1996, p.32-33 |
| issn | 0193-6530 2376-8606 |
| language | eng |
| recordid | cdi_ieee_primary_488501 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuit noise Circuit simulation Costs Flash memory Latches Pins Solid state circuit design Threshold voltage Throughput Voltage control |
| title | A 3.3 V 128 Mb multi-level NAND flash memory for mass storage applications |
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