Digital FIR filters for high speed PRML disk read channels

Digital FIR filters for high speed PRML disk read channels

This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design an...

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Veröffentlicht in:IEEE journal of solid-state circuits 1995-12, Vol.30 (12), p.1517-1523
Hauptverfasser: Pearson, D.J., Reynolds, S.K., Megdanis, A.C., Gowda, S., Wrenner, K.R., Immediato, M., Galbraith, R.L., Shin, H.J.
Format: Artikel
Sprache:eng
Schlagworte:
Adders
Arithmetic
Circuit synthesis
Design optimization
Digital filters
Finite impulse response filter
Latches
Partial response signaling
Sampling methods
Shift registers
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Beschreibung
Zusammenfassung:This paper presents 8-tap and 10-tap, 6-b filters designed to provide PR-IV channel equalization at data rates in excess of 20 megabyte/s. Achieving high sampling rates while reducing power and area required an optimized distributed-arithmetic (DA) architecture combined with custom circuit design and layout. These filters improve attainable data rate by 40% while reducing macro area by 20% compared with standard-cell-designed filters using the same architecture and technology.
ISSN:0018-9200
1558-173X
DOI:10.1109/4.482200