Neurocomputer with binary memory matrices for pattern recognition tasks

Neurocomputer with binary memory matrices for pattern recognition tasks

Algorithms, principle of operation, hardware, and test experiments of a neurocomputer, based on a large random access memory and parallel arithmetical logical units, are described. This paper describes the developments of the neurocomputer with binary memory matrices, that are made in Zelenograd.

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Bibliographische Detailangaben
Hauptverfasser: Dyabin, M.I., Karpinski, N.G., Polovyanyuk, A.I., Red'ko, V.G., Urgant, O.V.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Cybernetics
Hardware
Logic testing
Neural networks
Neurons
Pattern recognition
Random access memory
Read-write memory
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Beschreibung
Zusammenfassung:Algorithms, principle of operation, hardware, and test experiments of a neurocomputer, based on a large random access memory and parallel arithmetical logical units, are described. This paper describes the developments of the neurocomputer with binary memory matrices, that are made in Zelenograd.
DOI:10.1109/ISNINC.1995.480881