An ASIC design for decimation filter with canonic signed-digit representation

In this paper, we present a digital filter, which is used to establish an interface between oversampling sigma-delta modulator and direct torque controller (DTC), for closed-loop motor control system. The destination of this digital filter is to decrease the frequency spectrum and filtered out the feedback signal into the DTC. Note that the architecture of the proposed digital filter includes a 4-stage comb filters and a finite impulse response (FIR) filter. After the filtering function is verified with FPGA, the original Verilog code will be transformed into digital chip through the cell-based library design procedure with the TSMC 0.35 mum 2 P4 M process. The specification includes that the bias voltage, the chip area, and the power consumption are 3.3V, 2.30 times 2.29 mm 2 , and 16.1 mW, respectively.