Gate length scaling and high drive currents enabled for high performance SOI technology using high-κ/metal gate

CMOS devices with high-k/metal gate stacks have been fabricated using a gate-first process flow and conventional stressors at gate lengths of 25 nm, highlighting the scalability of this approach for high performance SOI CMOS technology. AC drive currents of 1630muA/mum and 1190muA/mum have been demo...

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Bibliographische Detailangaben

Hauptverfasser:	Henson, K., Bu, H., Na, M.H., Liang, Y., Kwon, U., Krishnan, S., Schaeffer, J., Jha, R., Moumen, N., Carter, R., DeWan, C., Donaton, R., Guo, D., Hargrove, M., He, W., Mo, R., Ramachandran, R., Ramani, K., Schonenberg, K., Tsang, Y., Wang, X., Gribelyuk, M., Yan, W., Shepard, J., Cartier, E., Frank, M., Harley, E., Arndt, R., Knarr, R., Bailey, T., Zhang, B., Wong, K., Graves-Abe, T., Luckowski, E., Park, D.-G., Narayanan, V., Chudzik, M., Khare, M.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	CMOS process CMOS technology Germanium silicon alloys Helium High K dielectric materials High-K gate dielectrics Research and development Scalability Silicon germanium Stress
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