Interface Traps in Silicon Carbide MOSFETs

In "classical" MOS technology, reliability and performance limiting defects are, as a rule, precisely at the semiconductor/insulator interface and very near that interface on the dielectric side. In the Si/SiO 2 system, the dominating defects have typically been silicon dangling bond defects. During the last few years there has been a great deal of interest in "new materials" based MOS technologies. In these new devices, the physical location and chemical nature of performance limiting defects may be very different from the Si/SiO 2 case. In this study we show that "interface traps" in 4H SiC MOSFETs may be very strongly influenced by the quality of the SiC substrate, with defects in that substrate present at densities which can be comparable to or in excess of the defect densities precisely at the semiconductor/ dielectric interface. Using DCIV and magnetic resonance measurements, we explore the physical location and chemical nature of these performance limiting defects in variously processed SiC MOSFETs.