The Challenges of On-Chip Protection for System Level Cable Discharge Events (CDE)

The Challenges of On-Chip Protection for System Level Cable Discharge Events (CDE)

The CDE stress for on-chip protection is evaluated with the design of a TI internal CDE tester. Comparison with a long-pulse TLP indicated non-correlation for the failure current but better tracking with the failure voltage. However, both the on-board magnetics and board design can also influence th...

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Bibliographische Detailangaben
Hauptverfasser: Yen-Yi Lin, Jae Park, Isachar, O., Chaikin, S., Chundru, R., Duvvury, C., Marum, S., Diep, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Communication cables
Ethernet networks
Power cables
Protection
Relays
Stress
System testing
System-on-a-chip
Transceivers
Wires
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Zusammenfassung:The CDE stress for on-chip protection is evaluated with the design of a TI internal CDE tester. Comparison with a long-pulse TLP indicated non-correlation for the failure current but better tracking with the failure voltage. However, both the on-board magnetics and board design can also influence the failure threshold level.