Integrated system development for 3-D VLSI

A great deal of effort worldwide is being put into 3-D VLSI development. Wafer stacking is one option for manufacturing, which is good for stacking device wafers of high yield, low heat dissipation, and homogenous materials. However, for applications with moderate yield layers, high power, and differing materials, wafer stacking methods may suffer from cumulative yield issues and potential reliablility problems. The University of Arkansas is developing a novel 3-D packaging technology by die stacking. TSVs are etched and filled with copper to provide electrical connections from the front to the back side of the wafer. Copper posts and dams are plated up and used to join an individual layer to the one next to it, by forming a copper-tin intermetalic. Electrical connections are thus formed, while micro-fluid channels for cooling are created between each pair of die. Coolant is pumped through the fluid channels in order to remove heat from individual dice. Known good die can be preselected before bonding in order to address the cumulative yield problem. The die are then joined using a typical flip chip bonder. Gold to gold thermal compression can also be used, in order to bond GaAs chips with gold metalization to the silicon structure. A two layer test vehicle was designed and built to demonstrate the process. Copper posts 30 mum and 50 mum in diameter and 100 mum high have been fabricated. Tin was electroplated on daisy chain links to ensure reliable joining. The test vehicle had good daisy-chain yield of post structures and the dam provided a leak-free fluid channel. We report here the results of this work. These results allowed us to proceed with a four-layer thermal test vehicle. The TSV technology, copper dam and post technology, and assembly technology are combined in the thermal test vehicle, in which heat dissipation resistors, meandering temperature sensing resistors, and various daisy chains are included. Following sequential flip chip assembly of all four layers, the structure will be mounted with manifolds and coolant will be circulated in the system so that thermal and reliability tests can be performed. Currently this four-layer structure is being fabricated on silicon. An automated test system which will be used to determine the thermal performance and reliability has been designed and tested.