High performance 3.3- and 5-V 0.5-/spl mu/m CMOS technology for ASIC's

Process integration of two manufacturable high performance 0.5-/spl mu/m CMOS technologies, one optimized for 5.0 V operation and the second optimized for 3.3-V operation, will be presented. The paper will emphasize poly-buffered LOGOS (PBL) isolation, MOS transistor design using conventional and st...

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Veröffentlicht in:	IEEE transactions on semiconductor manufacturing 1995-11, Vol.8 (4), p.440-448
Hauptverfasser:	Kizilyalli, I.C., Thoma, M.J., Lytle, S.A., Martin, E.P., Singh, R., Vitkavage, S.C., Bechtold, P.F., Kearney, J.W., Rambaud, M.M., Twiford, M.S., Cochran, W.T., Fenstermaker, L.R., Freyman, R., Weishi Sun, Duncan, A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuit optimization CMOS process CMOS technology Fluctuations Hot carriers Isolation technology Manufacturing processes MOSFETs Semiconductor device modeling Virtual manufacturing
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