High throughput 32-bit AES implementation in FPGA
Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper present...
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| creator | Chi-Jeng Chang Chi-Wu Huang Kuo-Huang Chang Yi-Cheng Chen Chung-Cheng Hsieh |
| description | Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature. |
| doi_str_mv | 10.1109/APCCAS.2008.4746393 |
| format | Conference Proceeding |
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However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.</abstract><pub>IEEE</pub><doi>10.1109/APCCAS.2008.4746393</doi><tpages>4</tpages></addata></record> |
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| identifier | ISBN: 9781424423415 |
| ispartof | APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, 2008, p.1806-1809 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Circuits Clocks Educational technology Electronics industry Field programmable gate arrays Hardware Industrial electronics Shift registers Table lookup Throughput |
| title | High throughput 32-bit AES implementation in FPGA |
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