High throughput 32-bit AES implementation in FPGA

High throughput 32-bit AES implementation in FPGA

Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper present...

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Bibliographische Detailangaben
Hauptverfasser: Chi-Jeng Chang, Chi-Wu Huang, Kuo-Huang Chang, Yi-Cheng Chen, Chung-Cheng Hsieh
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuits
Clocks
Educational technology
Electronics industry
Field programmable gate arrays
Hardware
Industrial electronics
Shift registers
Table lookup
Throughput
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Beschreibung
Zusammenfassung:Advance Encryption Standard (AES) hardware implementation in FPGA as well as in ASIC has been intensely discussing, especially in high-throughput (over several tens Gbps). However, low area designs have also been investigated in recent years for the embedded hardware applications. This paper presents a 32-bit AES implementation with a low area of 156 slices and a throughput of 876 Mbps, which outperformed the best reported result of 648 Mbps throughput found in literature.
DOI:10.1109/APCCAS.2008.4746393