Design optimization of a 10 GHz low noise amplifier with gate drain capacitance consideration in 65 nm CMOS technology

Most of papers have ignored the effect of gate-drain capacitance of transistor due to its complexity when they analyze a low noise amplifier circuit (LNA). However, as scaling down the CMOS technology, the ratio of gate-drain capacitance (C gd ) to gate-source capacitance (C gs ) increases. This phenomenon affects the input matching, power gain and noise figure of the LNA circuit. In this paper, we propose the circuit analysis with new analytic equations derived from equivalent circuit of LNA which considered the C gd effect. With this approach, the input power matching, overall trans-conductance and noise figure could be accurately calculated more than conventional equation. Moreover, a design approach is introduced to optimize the LNA circuit. Prior to fabrication of full LNA circuit, optimum bias and width could be determined to maximize FoM. This paper shows the guide line to design an LNA circuit at 10 GHz operating frequency using 65 nm technology.