The Design of Radix-4 FFT by FPGA
This paper designs and realizes a synthetic aperture radar (SAR) real-time processor by FPGA chip, Radix-4FFT is the kernel processing in compression algorithm of SAR; The memory organization of Radix-4 FFT is considered. The design of the block floating Radix-4 FFT is valuable in military and civil...
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| creator | Zhijian Sun Xuemei Liu Zhongxing Ji |
| description | This paper designs and realizes a synthetic aperture radar (SAR) real-time processor by FPGA chip, Radix-4FFT is the kernel processing in compression algorithm of SAR; The memory organization of Radix-4 FFT is considered. The design of the block floating Radix-4 FFT is valuable in military and civil application, and the complete of transpose is valuable for the later SAR real-time processing research. This paper analyses the performance advantages of using FPGA, and present the processing result of a frame of airborne SAR original data. |
| doi_str_mv | 10.1109/IITA.Workshops.2008.32 |
| format | Conference Proceeding |
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The design of the block floating Radix-4 FFT is valuable in military and civil application, and the complete of transpose is valuable for the later SAR real-time processing research. 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This paper analyses the performance advantages of using FPGA, and present the processing result of a frame of airborne SAR original data.</description><subject>Algorithm design and analysis</subject><subject>Compression algorithms</subject><subject>Design methodology</subject><subject>Digital signal processing</subject><subject>Digital signal processing chips</subject><subject>DSP</subject><subject>Field programmable gate arrays</subject><subject>FPGA chip</subject><subject>Hardware</subject><subject>Kernel</subject><subject>Radix-4 FFT</subject><subject>Read-write memory</subject><subject>real-time processor</subject><subject>Synthetic aperture radar</subject><subject>Synthetic Aperture Radar (SAR)</subject><isbn>0769535054</isbn><isbn>9780769535050</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotzMtKw0AUgOEBKWhrn0CQ8QESz2UmJ7MM1dRAQZGIy5J0Zmy8pWRc2LcX0dUP3-JX6hIhRwR33TRtlT-P01vaj4eUE0CZM52oOUjhLFuwZqbmv-zAlYKnapnSKwCgKwTZnqmrdh_0TUjDy6ceo37s_PCdGV3Xre6Pun5YV-dqFrv3FJb_Xain-rZd3WWb-3WzqjbZgGK_MkLH1oUgAMbvxJBFErDAxEJsC6DIPlAglIKjFYxldD3uvCdm6j0v1MXfdwghbA_T8NFNx60RJjCOfwAe_j1r</recordid><startdate>200812</startdate><enddate>200812</enddate><creator>Zhijian Sun</creator><creator>Xuemei Liu</creator><creator>Zhongxing Ji</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope></search><sort><creationdate>200812</creationdate><title>The Design of Radix-4 FFT by FPGA</title><author>Zhijian Sun ; Xuemei Liu ; Zhongxing Ji</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-219359ee7004dc74251270503237235602f3de2e21763f571f8f9b1cdd2332bd3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Algorithm design and analysis</topic><topic>Compression algorithms</topic><topic>Design methodology</topic><topic>Digital signal processing</topic><topic>Digital signal processing chips</topic><topic>DSP</topic><topic>Field programmable gate arrays</topic><topic>FPGA chip</topic><topic>Hardware</topic><topic>Kernel</topic><topic>Radix-4 FFT</topic><topic>Read-write memory</topic><topic>real-time processor</topic><topic>Synthetic aperture radar</topic><topic>Synthetic Aperture Radar (SAR)</topic><toplevel>online_resources</toplevel><creatorcontrib>Zhijian Sun</creatorcontrib><creatorcontrib>Xuemei Liu</creatorcontrib><creatorcontrib>Zhongxing Ji</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Zhijian Sun</au><au>Xuemei Liu</au><au>Zhongxing Ji</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>The Design of Radix-4 FFT by FPGA</atitle><btitle>2008 International Symposium on Intelligent Information Technology Application Workshops</btitle><stitle>IITAW</stitle><date>2008-12</date><risdate>2008</risdate><spage>765</spage><epage>768</epage><pages>765-768</pages><isbn>0769535054</isbn><isbn>9780769535050</isbn><abstract>This paper designs and realizes a synthetic aperture radar (SAR) real-time processor by FPGA chip, Radix-4FFT is the kernel processing in compression algorithm of SAR; The memory organization of Radix-4 FFT is considered. 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| ispartof | 2008 International Symposium on Intelligent Information Technology Application Workshops, 2008, p.765-768 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Algorithm design and analysis Compression algorithms Design methodology Digital signal processing Digital signal processing chips DSP Field programmable gate arrays FPGA chip Hardware Kernel Radix-4 FFT Read-write memory real-time processor Synthetic aperture radar Synthetic Aperture Radar (SAR) |
| title | The Design of Radix-4 FFT by FPGA |
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