BIST for embedded static RAMs with coverage calculation

The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs. Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strate...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	van Sas, J., Van Wauwe, G., Huyskens, E., Rabaey, D.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Application specific integrated circuits B-ISDN Built-in self-test Change detection algorithms Circuit faults Circuit testing Logic devices Logic testing Random access memory Read-write memory
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	The implementation of deterministic RAM self-test algorithms turns out to be very area-consuming when a single ASIC contains many small, deeply embedded RAMs. Therefore, we have opted to reuse and modify the existing functional logic and to use a combined deterministic pseudo-random self-test strategy. A novel fault coverage calculation method for this self-test strategy has been developed. The method is easy to use because it is fully integrated in a hardware description language based design environment. Results for a chip set for broadband ISDN show that the combination of pseudo-random data generation and deterministic addressing of the RAMs provides high fault coverage results. Circuitry overhead varies between 2 and 14% of the RAM surface.< >
DOI:	10.1109/TEST.1993.470679