Bit parallel test pattern generation for path delay faults

Bit parallel test pattern generation for path delay faults

A method to apply bit-parallel processing at all stages of robust and nonrobust test pattern generation for path delay faults is presented. Two different modes of bit-parallel processing are combined: fault parallel test pattern generation (FPTPG) and alternative parallel test pattern generation (AP...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Henftling, M., Wittman, H.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Circuit faults
Circuit simulation
Circuit testing
Delay effects
Fault detection
Latches
Logic testing
Robustness
System testing
Test pattern generators
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Beschreibung
Zusammenfassung:A method to apply bit-parallel processing at all stages of robust and nonrobust test pattern generation for path delay faults is presented. Two different modes of bit-parallel processing are combined: fault parallel test pattern generation (FPTPG) and alternative parallel test pattern generation (APTPG). We discuss the problems that appear while exploiting bit-parallelity and we describe how to overcome them. Experimental results demonstrate a reduction of aborted faults and an acceleration up to a factor of nine.< >
DOI:10.1109/EDTC.1995.470351