Supply-noise mitigation techniques in phase-locked loops

Supply-noise significantly affects the jitter performance of ring oscillator-based phase-locked loops (PLLs). While the focus of much of the prior art is on supply-noise in oscillators, this paper illustrates that supply-noise in other building blocks also contribute significantly to PLL output jitter. The current design employs a split-tuned PLL architecture wherein the power supply of the building blocks is derived from the regulated power supply of the VCO. The prototype PLL fabricated in a 0.18 mum digital CMOS process occupies 0.18 mm 2 and consumes only 3.3 mW, from a 1.8 V supply, of which 0.54 mW is consumed in the regulators, while operating at 1.5 GHz. The PLL achieves 33 ps and 41 ps peak-to-peak jitter with no supply noise and with 100 mV peak-to-peak supply noise, respectively.