A 512-KB level-2 cache design in 45-nm for low power IA processor silverthorne

A self-timed, phase based 512KB L2 cache design in 45 nm CMOS process for a low power IA core is presented. The design supports back to back access every core clock by performing sense amplifier (SA) evaluation and SA precharge (SAPCH) in one phase. Dynamic latch is used in the data-out path to enable the use of narrowest SA and latch pulse (LATCK) width during high volume manufacturing (HVM). Power gated (PG) WL driver, sleep and deep sleep for the SRAM array along with floating the bit lines and tri-state write driver schemes are implemented to reduce cache leakage power. The design meets the performance requirement of 2.0 GHz and 1.0 GHz at 1.0 V and 0.75 V respectively at 90C.