A continuous-time input pipeline ADC

A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution wit...

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Bibliographische Detailangaben
Hauptverfasser: Gubbins, David, Lee, Bumha, Hanumolu, Pavan Kumar, Un-Ku Moon
Format: Tagungsbericht
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18μm CMOS process validate the effectiveness of proposed techniques.
ISSN:0886-5930
DOI:10.1109/CICC.2008.4672050