A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

A process variation compensation scheme using cell-based forward body-biasing circuits usable for 1.2V design

A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with small area overhead. By applying this technique to a...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Tachibana, F., Sato, H., Yamashita, T., Hara, H., Kitahara, T., Nomura, S., Yamane, F., Tsuboi, Y., Seki, K., Matsumoto, S., Watanabe, Y., Hamada, M.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Bipolar transistors
Circuits
CMOS technology
Delay
Microelectronics
MOS devices
Power dissipation
Threshold voltage
Variable structure systems
Voltage control
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A cell-based forward body-biasing technique to suppress the global process variation and its design flow are proposed. Latch-up free operation is guaranteed by embedded current source cells and limiter cells even when supply voltage is 1.2 V with small area overhead. By applying this technique to a media processor, the worst-case delay is reduced by 20% without sacrificing the maximum leakage spec.
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2008.4672012