A Special-Purpose Architecture for Solving the Breakpoint Median Problem
In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our...
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Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2008-12, Vol.16 (12), p.1666-1676 |
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Sprache: | eng |
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Zusammenfassung: | In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median computation, which is an expensive component of the overall application. When implemented on a field-programmable gate array (FPGA), our hardware breakpoint median achieves a maximum speedup of 1005times over software. When the coprocessor is used to accelerate the entire reconstruction procedure, we achieve a maximum application speedup of 417times. The results in this paper suggest that FPGA-based acceleration is a promising approach for computationally expensive phylogenetic problems, in spite of the fact that the involved algorithms are based on complex, control-dependent combinatorial optimization. |
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ISSN: | 1063-8210 1557-9999 |
DOI: | 10.1109/TVLSI.2008.2001298 |