Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology
A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance...
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| Veröffentlicht in: | IEEE transactions on electron devices 2008-11, Vol.55 (11), p.3208-3213 |
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| container_end_page | 3213 |
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| container_issue | 11 |
| container_start_page | 3208 |
| container_title | IEEE transactions on electron devices |
| container_volume | 55 |
| creator | HSU, Heng-Ming CHAN, Kai-Yuen CHIEN, Hung-Chi KUAN, Han-Chien |
| description | A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high- Q inductor for RFIC applications. |
| doi_str_mv | 10.1109/TED.2008.2004248 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_ieee_primary_4668566</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4668566</ieee_id><sourcerecordid>34510581</sourcerecordid><originalsourceid>FETCH-LOGICAL-c384t-1744861a569563536ce26fb49fe8703c10604c7db03fbdda941290196c56c8123</originalsourceid><addsrcrecordid>eNp9kc1rGzEQxUVoIG7SeyEXEWjJZRONPmalo3E-wSGBumchy1pnw3qVSrsH__eVsckhh1xmGOb3huE9Qn4CuwJg5npxe3PFGdO7IrnUR2QCStWVQYnfyIQx0JURWpyQ7zm_lRGl5BPyMO1dtx1a7zp6E3K77um0W8fUDq8bGhv60rneJfrYr0Y_xETnbhvHgbY9nT09_6GL4F_72MX19owcN67L4cehn5K_d7eL2UM1f75_nE3nlRdaDhXUUmoEp9AoFEqgDxybpTRN0DUTHhgy6evVkolmuVo5I4EbBga9Qq-Bi1Pye3_3PcV_Y8iD3bTZh678GeKYrZAKmNJQwMsvQcAahOAKdujFJ_QtjqkYk61GLpXkWBeI7SGfYs4pNPY9tRuXthaY3UVgSwR2F4E9RFAkvw53XS4GN8n1vs0fOs60MrVhhTvfc20I4WMtEbVCFP8B0tKLkQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>862454267</pqid></control><display><type>article</type><title>Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology</title><source>IEEE Electronic Library (IEL)</source><creator>HSU, Heng-Ming ; CHAN, Kai-Yuen ; CHIEN, Hung-Chi ; KUAN, Han-Chien</creator><creatorcontrib>HSU, Heng-Ming ; CHAN, Kai-Yuen ; CHIEN, Hung-Chi ; KUAN, Han-Chien</creatorcontrib><description>A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high- Q inductor for RFIC applications.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2008.2004248</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Algorithms ; Analytical algorithm ; Applied sciences ; Chip formation ; CMOS ; CMOS integrated circuits ; CMOS technology ; Coiling ; Design. Technologies. Operation analysis. Testing ; Devices ; Electronics ; Exact sciences and technology ; Inductance ; Inductors ; Integrated circuits ; Layout ; Magnetic devices ; Mathematical analysis ; minimum resistance ; on-chip inductor ; Radiofrequency integrated circuits ; Resistance ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; variable width</subject><ispartof>IEEE transactions on electron devices, 2008-11, Vol.55 (11), p.3208-3213</ispartof><rights>2008 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2008</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c384t-1744861a569563536ce26fb49fe8703c10604c7db03fbdda941290196c56c8123</citedby><cites>FETCH-LOGICAL-c384t-1744861a569563536ce26fb49fe8703c10604c7db03fbdda941290196c56c8123</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4668566$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4668566$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=20859790$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>HSU, Heng-Ming</creatorcontrib><creatorcontrib>CHAN, Kai-Yuen</creatorcontrib><creatorcontrib>CHIEN, Hung-Chi</creatorcontrib><creatorcontrib>KUAN, Han-Chien</creatorcontrib><title>Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high- Q inductor for RFIC applications.</description><subject>Algorithms</subject><subject>Analytical algorithm</subject><subject>Applied sciences</subject><subject>Chip formation</subject><subject>CMOS</subject><subject>CMOS integrated circuits</subject><subject>CMOS technology</subject><subject>Coiling</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Devices</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Inductance</subject><subject>Inductors</subject><subject>Integrated circuits</subject><subject>Layout</subject><subject>Magnetic devices</subject><subject>Mathematical analysis</subject><subject>minimum resistance</subject><subject>on-chip inductor</subject><subject>Radiofrequency integrated circuits</subject><subject>Resistance</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>variable width</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2008</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kc1rGzEQxUVoIG7SeyEXEWjJZRONPmalo3E-wSGBumchy1pnw3qVSrsH__eVsckhh1xmGOb3huE9Qn4CuwJg5npxe3PFGdO7IrnUR2QCStWVQYnfyIQx0JURWpyQ7zm_lRGl5BPyMO1dtx1a7zp6E3K77um0W8fUDq8bGhv60rneJfrYr0Y_xETnbhvHgbY9nT09_6GL4F_72MX19owcN67L4cehn5K_d7eL2UM1f75_nE3nlRdaDhXUUmoEp9AoFEqgDxybpTRN0DUTHhgy6evVkolmuVo5I4EbBga9Qq-Bi1Pye3_3PcV_Y8iD3bTZh678GeKYrZAKmNJQwMsvQcAahOAKdujFJ_QtjqkYk61GLpXkWBeI7SGfYs4pNPY9tRuXthaY3UVgSwR2F4E9RFAkvw53XS4GN8n1vs0fOs60MrVhhTvfc20I4WMtEbVCFP8B0tKLkQ</recordid><startdate>20081101</startdate><enddate>20081101</enddate><creator>HSU, Heng-Ming</creator><creator>CHAN, Kai-Yuen</creator><creator>CHIEN, Hung-Chi</creator><creator>KUAN, Han-Chien</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>97E</scope><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20081101</creationdate><title>Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology</title><author>HSU, Heng-Ming ; CHAN, Kai-Yuen ; CHIEN, Hung-Chi ; KUAN, Han-Chien</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c384t-1744861a569563536ce26fb49fe8703c10604c7db03fbdda941290196c56c8123</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Algorithms</topic><topic>Analytical algorithm</topic><topic>Applied sciences</topic><topic>Chip formation</topic><topic>CMOS</topic><topic>CMOS integrated circuits</topic><topic>CMOS technology</topic><topic>Coiling</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Devices</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Inductance</topic><topic>Inductors</topic><topic>Integrated circuits</topic><topic>Layout</topic><topic>Magnetic devices</topic><topic>Mathematical analysis</topic><topic>minimum resistance</topic><topic>on-chip inductor</topic><topic>Radiofrequency integrated circuits</topic><topic>Resistance</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>variable width</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>HSU, Heng-Ming</creatorcontrib><creatorcontrib>CHAN, Kai-Yuen</creatorcontrib><creatorcontrib>CHIEN, Hung-Chi</creatorcontrib><creatorcontrib>KUAN, Han-Chien</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 2005-present</collection><collection>IEEE All-Society Periodicals Package (ASPP) 1998–Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HSU, Heng-Ming</au><au>CHAN, Kai-Yuen</au><au>CHIEN, Hung-Chi</au><au>KUAN, Han-Chien</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2008-11-01</date><risdate>2008</risdate><volume>55</volume><issue>11</issue><spage>3208</spage><epage>3213</epage><pages>3208-3213</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high- Q inductor for RFIC applications.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2008.2004248</doi><tpages>6</tpages></addata></record> |
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| issn | 0018-9383 1557-9646 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Algorithms Analytical algorithm Applied sciences Chip formation CMOS CMOS integrated circuits CMOS technology Coiling Design. Technologies. Operation analysis. Testing Devices Electronics Exact sciences and technology Inductance Inductors Integrated circuits Layout Magnetic devices Mathematical analysis minimum resistance on-chip inductor Radiofrequency integrated circuits Resistance Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices variable width |
| title | Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T17%3A14%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analytical%20Design%20Algorithm%20of%20Planar%20Inductor%20Layout%20in%20CMOS%20Technology&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=HSU,%20Heng-Ming&rft.date=2008-11-01&rft.volume=55&rft.issue=11&rft.spage=3208&rft.epage=3213&rft.pages=3208-3213&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2008.2004248&rft_dat=%3Cproquest_RIE%3E34510581%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=862454267&rft_id=info:pmid/&rft_ieee_id=4668566&rfr_iscdi=true |