Analytical Design Algorithm of Planar Inductor Layout in CMOS Technology

A layout design algorithm for a variable-width inductor is proposed to minimize metal resistance. For a given chip area, the proposed algorithm can rapidly design metal widths of each coil in a planar inductor due to the analytical form. Two on-chip inductors with identical chip areas and inductance are fabricated to verify the proposed method in foundry 90-nm CMOS technology. Measurement results demonstrate that the improvement of metal resistance in the proposed device is approximately 19%. The results of this paper provide an effective algorithm to design a high- Q inductor for RFIC applications.