A mapping algorithm for embedded coarse-grained reconfigurable processor

A mapping algorithm for embedded coarse-grained reconfigurable processor

This paper proposes a novel VLSI architecture of an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained reconfigurable cell array (RCA). This processor can be reconfigured dynamically targeted at different media-processing applications. An alg...

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Hauptverfasser: Sudong Yu, Leibo Liu, Shouyi Yin, Shaojun Wei
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Sprache:eng
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Computer architecture
Digital signal processing
Discrete cosine transforms
Equations
Field programmable gate arrays
Mathematical model
Pipelines
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Leibo Liu
Shouyi Yin
Shaojun Wei
description This paper proposes a novel VLSI architecture of an embedded coarse-grained reconfigurable processor, which consists of a general processor and a coarse-grained reconfigurable cell array (RCA). This processor can be reconfigured dynamically targeted at different media-processing applications. An algorithm based on loop pipeline technology is presented to address the compilation issue for the proposed architecture, which can effectively maps the computation intensive loops onto the RCA. The proposed VLSI architecture and the mapping algorithm have been verified with integer discrete cosine transform (DCT) and motion estimation of H.264 in FPGA. The performance of the reconfigurable processor is 3.81 times better than TI DSP TMS320DM642.
doi_str_mv 10.1109/ICCCAS.2008.4657959
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subjects Computer architecture
Digital signal processing
Discrete cosine transforms
Equations
Field programmable gate arrays
Mathematical model
Pipelines
title A mapping algorithm for embedded coarse-grained reconfigurable processor
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