An advanced model for calculating the effective capacitance considering input waveform effect

In deep submicron designs, predicting gate delays is a noteworthy work for static timing analysis (STA). The effective capacitance C eff concept is usually used to calculate the gate delay of interconnect load. Conventionally, the input-signal is assumed as ramp waveform. However, the input waveform is also the output of CMOS gates with interconnect wires. Thus the simple assumption as a ramp signal results in significant influence on the delay calculating. In this paper, an advanced effective capacitance model is proposed to consider both the input waveform effect and interconnect wire load, where the nonlinear influence of input waveform is modeled as one part of effective capacitance of capacitive load to compute the gate delay. Experimental results show a significant improvement in accuracy when the input waveform effect is considered.