A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel
In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip...
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| creator | Minchul Shin Jongjoo Shim Jaemin Kim Jun So Pak Chulsoon Hwang Changwook Yoon Kim, Joungho Hyungsoo Kim Kunwoo Park Yongju Kim |
| description | In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm. |
| doi_str_mv | 10.1109/ISEMC.2008.4652099 |
| format | Conference Proceeding |
| fullrecord | <record><control><sourceid>ieee_6IE</sourceid><recordid>TN_cdi_ieee_primary_4652099</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4652099</ieee_id><sourcerecordid>4652099</sourcerecordid><originalsourceid>FETCH-LOGICAL-i90t-7601be8d4367af835a3b082c5b47db34db9758546aa488808107df989e8c2963</originalsourceid><addsrcrecordid>eNpVkMtqwzAURNVHoCHND7Qb_YDdK-vhq2UwaRpI6SJddBdkW7ZVHNlY7sJ_X0NCoauZ4cAMDCFPDGLGQL_sj9v3LE4AMBZKJqD1DVnrFJlIhGBKI7sly4RJjBhjePePabz_Y_C1IEvkkRJSCP1A1iF8A8A8oTRnS2I2VMVil_eBdj4qGtdTO1na9dY7X9Nz593YDbRwQ_HjRlrNPrjam5Y6P9p6cONEzRyn4OaGijaubmjorS1p0RjvbftIFpVpg11fdUWOr9vP7C06fOz22eYQOQ1jlCpgucVScJWaCrk0PAdMCpmLtMy5KHOdSpRCGSMQEZBBWlYatcUi0YqvyPOl1VlrT_3gzmaYTtfr-C_v-1tR</addsrcrecordid><sourcetype>Publisher</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype></control><display><type>conference_proceeding</type><title>A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Minchul Shin ; Jongjoo Shim ; Jaemin Kim ; Jun So Pak ; Chulsoon Hwang ; Changwook Yoon ; Kim, Joungho ; Hyungsoo Kim ; Kunwoo Park ; Yongju Kim</creator><creatorcontrib>Minchul Shin ; Jongjoo Shim ; Jaemin Kim ; Jun So Pak ; Chulsoon Hwang ; Changwook Yoon ; Kim, Joungho ; Hyungsoo Kim ; Kunwoo Park ; Yongju Kim</creatorcontrib><description>In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.</description><identifier>ISSN: 2158-110X</identifier><identifier>ISBN: 9781424416998</identifier><identifier>ISBN: 142441699X</identifier><identifier>EISSN: 2158-1118</identifier><identifier>EISBN: 9781424416981</identifier><identifier>EISBN: 1424416981</identifier><identifier>DOI: 10.1109/ISEMC.2008.4652099</identifier><identifier>LCCN: 83-645449</identifier><language>eng</language><publisher>IEEE</publisher><subject>Clocks ; Delay ; Eye diagram ; Eye opening monitor ; high resolution ; high speed channel ; Integrated circuit modeling ; Monitoring ; on-die termination ; Signal analysis ; signal integrity ; System-on-a-chip ; Voltage control</subject><ispartof>2008 IEEE International Symposium on Electromagnetic Compatibility, 2008, p.1-6</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4652099$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,2052,27906,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4652099$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Minchul Shin</creatorcontrib><creatorcontrib>Jongjoo Shim</creatorcontrib><creatorcontrib>Jaemin Kim</creatorcontrib><creatorcontrib>Jun So Pak</creatorcontrib><creatorcontrib>Chulsoon Hwang</creatorcontrib><creatorcontrib>Changwook Yoon</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><creatorcontrib>Hyungsoo Kim</creatorcontrib><creatorcontrib>Kunwoo Park</creatorcontrib><creatorcontrib>Yongju Kim</creatorcontrib><title>A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel</title><title>2008 IEEE International Symposium on Electromagnetic Compatibility</title><addtitle>ISEMC</addtitle><description>In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.</description><subject>Clocks</subject><subject>Delay</subject><subject>Eye diagram</subject><subject>Eye opening monitor</subject><subject>high resolution</subject><subject>high speed channel</subject><subject>Integrated circuit modeling</subject><subject>Monitoring</subject><subject>on-die termination</subject><subject>Signal analysis</subject><subject>signal integrity</subject><subject>System-on-a-chip</subject><subject>Voltage control</subject><issn>2158-110X</issn><issn>2158-1118</issn><isbn>9781424416998</isbn><isbn>142441699X</isbn><isbn>9781424416981</isbn><isbn>1424416981</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtqwzAURNVHoCHND7Qb_YDdK-vhq2UwaRpI6SJddBdkW7ZVHNlY7sJ_X0NCoauZ4cAMDCFPDGLGQL_sj9v3LE4AMBZKJqD1DVnrFJlIhGBKI7sly4RJjBhjePePabz_Y_C1IEvkkRJSCP1A1iF8A8A8oTRnS2I2VMVil_eBdj4qGtdTO1na9dY7X9Nz593YDbRwQ_HjRlrNPrjam5Y6P9p6cONEzRyn4OaGijaubmjorS1p0RjvbftIFpVpg11fdUWOr9vP7C06fOz22eYQOQ1jlCpgucVScJWaCrk0PAdMCpmLtMy5KHOdSpRCGSMQEZBBWlYatcUi0YqvyPOl1VlrT_3gzmaYTtfr-C_v-1tR</recordid><startdate>200808</startdate><enddate>200808</enddate><creator>Minchul Shin</creator><creator>Jongjoo Shim</creator><creator>Jaemin Kim</creator><creator>Jun So Pak</creator><creator>Chulsoon Hwang</creator><creator>Changwook Yoon</creator><creator>Kim, Joungho</creator><creator>Hyungsoo Kim</creator><creator>Kunwoo Park</creator><creator>Yongju Kim</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200808</creationdate><title>A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel</title><author>Minchul Shin ; Jongjoo Shim ; Jaemin Kim ; Jun So Pak ; Chulsoon Hwang ; Changwook Yoon ; Kim, Joungho ; Hyungsoo Kim ; Kunwoo Park ; Yongju Kim</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i90t-7601be8d4367af835a3b082c5b47db34db9758546aa488808107df989e8c2963</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Clocks</topic><topic>Delay</topic><topic>Eye diagram</topic><topic>Eye opening monitor</topic><topic>high resolution</topic><topic>high speed channel</topic><topic>Integrated circuit modeling</topic><topic>Monitoring</topic><topic>on-die termination</topic><topic>Signal analysis</topic><topic>signal integrity</topic><topic>System-on-a-chip</topic><topic>Voltage control</topic><toplevel>online_resources</toplevel><creatorcontrib>Minchul Shin</creatorcontrib><creatorcontrib>Jongjoo Shim</creatorcontrib><creatorcontrib>Jaemin Kim</creatorcontrib><creatorcontrib>Jun So Pak</creatorcontrib><creatorcontrib>Chulsoon Hwang</creatorcontrib><creatorcontrib>Changwook Yoon</creatorcontrib><creatorcontrib>Kim, Joungho</creatorcontrib><creatorcontrib>Hyungsoo Kim</creatorcontrib><creatorcontrib>Kunwoo Park</creatorcontrib><creatorcontrib>Yongju Kim</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Minchul Shin</au><au>Jongjoo Shim</au><au>Jaemin Kim</au><au>Jun So Pak</au><au>Chulsoon Hwang</au><au>Changwook Yoon</au><au>Kim, Joungho</au><au>Hyungsoo Kim</au><au>Kunwoo Park</au><au>Yongju Kim</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel</atitle><btitle>2008 IEEE International Symposium on Electromagnetic Compatibility</btitle><stitle>ISEMC</stitle><date>2008-08</date><risdate>2008</risdate><spage>1</spage><epage>6</epage><pages>1-6</pages><issn>2158-110X</issn><eissn>2158-1118</eissn><isbn>9781424416998</isbn><isbn>142441699X</isbn><eisbn>9781424416981</eisbn><eisbn>1424416981</eisbn><abstract>In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.</abstract><pub>IEEE</pub><doi>10.1109/ISEMC.2008.4652099</doi><tpages>6</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 2158-110X |
| ispartof | 2008 IEEE International Symposium on Electromagnetic Compatibility, 2008, p.1-6 |
| issn | 2158-110X 2158-1118 |
| language | eng |
| recordid | cdi_ieee_primary_4652099 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Clocks Delay Eye diagram Eye opening monitor high resolution high speed channel Integrated circuit modeling Monitoring on-die termination Signal analysis signal integrity System-on-a-chip Voltage control |
| title | A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-21T06%3A25%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-ieee_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=A%206.4Gbps%20on-chip%20eye%20opening%20monitor%20circuit%20for%20signal%20integrity%20analysis%20of%20high%20speed%20channel&rft.btitle=2008%20IEEE%20International%20Symposium%20on%20Electromagnetic%20Compatibility&rft.au=Minchul%20Shin&rft.date=2008-08&rft.spage=1&rft.epage=6&rft.pages=1-6&rft.issn=2158-110X&rft.eissn=2158-1118&rft.isbn=9781424416998&rft.isbn_list=142441699X&rft_id=info:doi/10.1109/ISEMC.2008.4652099&rft_dat=%3Cieee_6IE%3E4652099%3C/ieee_6IE%3E%3Curl%3E%3C/url%3E&rft.eisbn=9781424416981&rft.eisbn_list=1424416981&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rft_ieee_id=4652099&rfr_iscdi=true |