A 6.4Gbps on-chip eye opening monitor circuit for signal integrity analysis of high speed channel

In this paper, an on-chip eye opening monitor circuit has been proposed with 4ps time and 4mv voltage resolutions for analyzing signal integrity of on-chip high speed channel. The proposed eye opening monitor circuit can detect the maximum 6.4Gbps data rate and give eye diagrams depending on on-chip high speed channel conditions. The performance of the proposed eye opening monitor circuit was verified by using a general spice simulations and showed the variations of eye diagram of 6.4 Gbps random data when on-die terminations of on-chip high speed channel was changed from 50 ohm to 80 ohm.