SPP1148 booth: Seamless design flow for reconfigurable systems

Today, using dynamic partial reconfiguration of FPGAs leads to a longer and less predictable design cycle. To improve this, we developed a modelling, simulation, and synthesis framework for partial reconfiguration, named OSSS+R. It reduces design time and hides some of the complexity. The tool PART-E integrates the results into the Xilinx early access partial reconfiguration (EAPR) flow. It eases floorplanning, bus macro instantiation, and bitstream generation. We show OSSS+R modelling, simulation and Part-E in a hands-on fashion. Synthesis to VHDL is demonstrated, too.