Fault-Tolerant Circuit for Carbon Nanotube Transistors with Si-CMOS Hybrid Circuitry

This paper presents the concept of a robust hybrid circuit in which reliable Si-CMOS circuits support the unreliable carbon nanotube-based circuit. We fabricated a test circuit and demonstrated the recovering operation from timing errors caused by delay variation of carbon nanotube transistors. We also estimated the overhead of the hybrid circuit, and confirmed by simulation that the delay overhead of the Si-CMOS part is small compared to the total delay.