Enhancing parallel-prefix structures using carry-save notation

Enhancing parallel-prefix structures using carry-save notation

Parallel prefix adders draw much attention because of their logarithmic delay. This paper proposes a scheme to enhance parallel prefix adders by incorporating the idea of carry-save addition within the prefix tree. Results are given for several designs using a publicly available nanometer library.

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Bibliographische Detailangaben
Hauptverfasser: Chen, J., Stine, J.E.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Adders
Computer architecture
DH-HEMTs
Equations
Logic gates
Mathematical model
Wire
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Beschreibung
Zusammenfassung:Parallel prefix adders draw much attention because of their logarithmic delay. This paper proposes a scheme to enhance parallel prefix adders by incorporating the idea of carry-save addition within the prefix tree. Results are given for several designs using a publicly available nanometer library.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2008.4616809