Flexible decoder architectures for irregular QC-LDPC codes

Flexible decoder architectures for irregular QC-LDPC codes

A flexible and power-efficient decoder architecture employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented in this paper. The architecture is verified by implementing a programmable decoder chip co...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: Tzu Chieh Kuo, Willson, A.N.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Computer architecture
Decoding
Memory management
Parity check codes
Prototypes
Throughput
WiMAX
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Beschreibung
Zusammenfassung:A flexible and power-efficient decoder architecture employing the layered-decoding message-passing algorithm and the low-complexity offset-based Min-Sum check algorithm for irregular QC-LDPC codes is presented in this paper. The architecture is verified by implementing a programmable decoder chip compliant with the QC-LDPC codes in Mobile WiMAX standard. Compared to other published decoder implementations, the prototype decoder is 53% smaller and has better energy efficiency.
ISSN:1548-3746
1558-3899
DOI:10.1109/MWSCAS.2008.4616778