Small-signal modeling of DC converters with digital peak-current-mode control
In this paper, an S-domain small-signal model is proposed for a buck converter with digital peak-current-mode (DPCM) control. This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for...
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creator | Hung-Shou Nien Dan Chen Wei-Hsu Chang |
description | In this paper, an S-domain small-signal model is proposed for a buck converter with digital peak-current-mode (DPCM) control. This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for designing the digital compensator and the prediction of control performance of DPCM converters. The problems with delay effect and the limit-cycle instability unique to digital control were addressed in the context of a DPCM converter. The model also allows one to predict the practical limit of a DPCM converter. A synchronous buck converter with digital peak-current-mode control using a field-programmable-gate-array (FPGA) has been built to verify the proposed model. The model can easily be extended to other digitally controlled power converter configurations. |
doi_str_mv | 10.1109/PESC.2008.4592457 |
format | Conference Proceeding |
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This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for designing the digital compensator and the prediction of control performance of DPCM converters. The problems with delay effect and the limit-cycle instability unique to digital control were addressed in the context of a DPCM converter. The model also allows one to predict the practical limit of a DPCM converter. A synchronous buck converter with digital peak-current-mode control using a field-programmable-gate-array (FPGA) has been built to verify the proposed model. The model can easily be extended to other digitally controlled power converter configurations.</description><identifier>ISSN: 0275-9306</identifier><identifier>ISBN: 9781424416677</identifier><identifier>ISBN: 1424416671</identifier><identifier>EISSN: 2377-6617</identifier><identifier>EISBN: 9781424416684</identifier><identifier>EISBN: 142441668X</identifier><identifier>DOI: 10.1109/PESC.2008.4592457</identifier><identifier>LCCN: 80-646675</identifier><language>eng</language><publisher>IEEE</publisher><subject>Converters ; Delay ; Gain ; Inductors ; Transfer functions ; Voltage control ; Voltage measurement</subject><ispartof>2008 IEEE Power Electronics Specialists Conference, 2008, p.3266-3271</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4592457$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,776,780,785,786,2052,27904,54898</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4592457$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Hung-Shou Nien</creatorcontrib><creatorcontrib>Dan Chen</creatorcontrib><creatorcontrib>Wei-Hsu Chang</creatorcontrib><title>Small-signal modeling of DC converters with digital peak-current-mode control</title><title>2008 IEEE Power Electronics Specialists Conference</title><addtitle>PESC</addtitle><description>In this paper, an S-domain small-signal model is proposed for a buck converter with digital peak-current-mode (DPCM) control. This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for designing the digital compensator and the prediction of control performance of DPCM converters. The problems with delay effect and the limit-cycle instability unique to digital control were addressed in the context of a DPCM converter. The model also allows one to predict the practical limit of a DPCM converter. A synchronous buck converter with digital peak-current-mode control using a field-programmable-gate-array (FPGA) has been built to verify the proposed model. The model can easily be extended to other digitally controlled power converter configurations.</description><subject>Converters</subject><subject>Delay</subject><subject>Gain</subject><subject>Inductors</subject><subject>Transfer functions</subject><subject>Voltage control</subject><subject>Voltage measurement</subject><issn>0275-9306</issn><issn>2377-6617</issn><isbn>9781424416677</isbn><isbn>1424416671</isbn><isbn>9781424416684</isbn><isbn>142441668X</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNpVkMtOwzAURM2jEqH0AxCb_IDLtX197SxRKA-pCKTCunISpxjSpHJCEX9PK7phNdLMmVkMY5cCpkJAdv0yW-RTCWCnqDOJ2hyxSWasQIkoiCwes0QqYziRMCf_MmNOWQLSaJ4poBFLLHDCna_P2HnffwBoJUAn7Gmxdk3D-7BqXZOuu8o3oV2lXZ3e5mnZtVsfBx_79DsM72kVVmHYYRvvPnn5FaNvB77v7Mkhds0FG9Wu6f3koGP2djd7zR_4_Pn-Mb-Z8yCMHjjaSmckCkPWqUJojaVG2JlSgizBW6nqUhUoS21qqqhQ4AHIEWFVC6zUmF397Qbv_XITw9rFn-XhJfULAmxUGg</recordid><startdate>200806</startdate><enddate>200806</enddate><creator>Hung-Shou Nien</creator><creator>Dan Chen</creator><creator>Wei-Hsu Chang</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200806</creationdate><title>Small-signal modeling of DC converters with digital peak-current-mode control</title><author>Hung-Shou Nien ; Dan Chen ; Wei-Hsu Chang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-48d5961b768a3b1554c5408d52202c0e823fc3b42c57f6d6b30e006a664df14d3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>Converters</topic><topic>Delay</topic><topic>Gain</topic><topic>Inductors</topic><topic>Transfer functions</topic><topic>Voltage control</topic><topic>Voltage measurement</topic><toplevel>online_resources</toplevel><creatorcontrib>Hung-Shou Nien</creatorcontrib><creatorcontrib>Dan Chen</creatorcontrib><creatorcontrib>Wei-Hsu Chang</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hung-Shou Nien</au><au>Dan Chen</au><au>Wei-Hsu Chang</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Small-signal modeling of DC converters with digital peak-current-mode control</atitle><btitle>2008 IEEE Power Electronics Specialists Conference</btitle><stitle>PESC</stitle><date>2008-06</date><risdate>2008</risdate><spage>3266</spage><epage>3271</epage><pages>3266-3271</pages><issn>0275-9306</issn><eissn>2377-6617</eissn><isbn>9781424416677</isbn><isbn>1424416671</isbn><eisbn>9781424416684</eisbn><eisbn>142441668X</eisbn><abstract>In this paper, an S-domain small-signal model is proposed for a buck converter with digital peak-current-mode (DPCM) control. This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for designing the digital compensator and the prediction of control performance of DPCM converters. The problems with delay effect and the limit-cycle instability unique to digital control were addressed in the context of a DPCM converter. The model also allows one to predict the practical limit of a DPCM converter. A synchronous buck converter with digital peak-current-mode control using a field-programmable-gate-array (FPGA) has been built to verify the proposed model. The model can easily be extended to other digitally controlled power converter configurations.</abstract><pub>IEEE</pub><doi>10.1109/PESC.2008.4592457</doi><tpages>6</tpages></addata></record> |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Converters Delay Gain Inductors Transfer functions Voltage control Voltage measurement |
title | Small-signal modeling of DC converters with digital peak-current-mode control |
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