Small-signal modeling of DC converters with digital peak-current-mode control

In this paper, an S-domain small-signal model is proposed for a buck converter with digital peak-current-mode (DPCM) control. This model is easily understandable and practically useful for power electronic engineers familiar with DC/DC converters using traditional analog control. It can be used for designing the digital compensator and the prediction of control performance of DPCM converters. The problems with delay effect and the limit-cycle instability unique to digital control were addressed in the context of a DPCM converter. The model also allows one to predict the practical limit of a DPCM converter. A synchronous buck converter with digital peak-current-mode control using a field-programmable-gate-array (FPGA) has been built to verify the proposed model. The model can easily be extended to other digitally controlled power converter configurations.