SIMD array on FPGA for B/W image processing
This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provide...
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| creator | Nieto, A. Brea, V.M. Vilarino, D.L. |
| description | This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 times 48 array on larger FPGAs. |
| doi_str_mv | 10.1109/CNNA.2008.4588678 |
| format | Conference Proceeding |
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The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 times 48 array on larger FPGAs.</abstract><pub>IEEE</pub><doi>10.1109/CNNA.2008.4588678</doi><tpages>6</tpages></addata></record> |
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| identifier | ISSN: 2165-0144 |
| ispartof | 2008 11th International Workshop on Cellular Neural Networks and Their Applications, 2008, p.202-207 |
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| language | eng |
| recordid | cdi_ieee_primary_4588678 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Arrays Clocks Field programmable gate arrays Image edge detection Logic gates Multiplexing Process control |
| title | SIMD array on FPGA for B/W image processing |
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