SIMD array on FPGA for B/W image processing

SIMD array on FPGA for B/W image processing

This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provide...

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Bibliographische Detailangaben
Hauptverfasser: Nieto, A., Brea, V.M., Vilarino, D.L.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Arrays
Clocks
Field programmable gate arrays
Image edge detection
Logic gates
Multiplexing
Process control
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Beschreibung
Zusammenfassung:This paper introduces a topographic implementation of an SIMD array for B/W image processing of 48 times 48 processing elements on an FPGA. The computation is done with Boolean and shift operators. The connectivity among processing elements is set through the classical NEWS system. The array provides the functionality of a CNNUM. The paper shows examples of algorithms and applications, and it also examines possible upscalings of the 48 times 48 array on larger FPGAs.
ISSN:2165-0144
2165-0152
DOI:10.1109/CNNA.2008.4588678