45nm low-power CMOS SoC technology with aggressive reduction of random variation for SRAM and analog transistors

Mobile system-on-chip (SoC) technologies require high-quality analog active and passive components along with low-power CMOS and dense SRAM. However, area scaling for both the SRAM bit cell and analog CMOS circuits is becoming increasingly difficult due to the impact of transistor random variation. To avoid added cost, co-optimizing the process for low random variation along with high performance and low power is required. We report a 45 nm lowpower technology with significantly reduced random variation for high yielding 0.255 mum 2 SRAM arrays and analog transistors. Flexible RF and passive components for mobile SoCpsilas are also described. These process techniques enable continued 50% area scaling at 45 nm and beyond.