A direct comparison of Josephson Array Voltage Standards

A number of direct comparisons of Josephson Array Voltage Standards (JAVS) using Superconductor-Insulator-Superconductor (SIS) junction arrays have been performed at the National Metrology Centre (NMC), Singapore. The comparisons were performed over a range of voltage from 1 V to 10 V and with diffe...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Liu, L.X., Chua, S.W., Lee, J., Zhou, Y., Hamilton, C.A.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:A number of direct comparisons of Josephson Array Voltage Standards (JAVS) using Superconductor-Insulator-Superconductor (SIS) junction arrays have been performed at the National Metrology Centre (NMC), Singapore. The comparisons were performed over a range of voltage from 1 V to 10 V and with different combinations of array chips, both USA and German made. The comparisons used a parallel biasing method that made it relatively easy to quickly bias both arrays on a nearly matched quantum step. The Type-A uncertainty of the difference voltage was typically lower than 1.5 nV.
ISSN:0589-1485
2160-0171
DOI:10.1109/CPEM.2008.4574806