A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

A behavioral synthesis method for asynchronous circuits with bundled-data implementation (Tool paper)

This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a rest...

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Hauptverfasser: Hamada, N., Shiga, Y., Saito, H., Yoneda, T., Myers, C., Nanya, T.
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Asynchronous circuits
Circuit synthesis
Clocks
Control system synthesis
Informatics
Processor scheduling
Resource management
Scheduling algorithm
Signal synthesis
Space exploration
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Beschreibung
Zusammenfassung:This paper presents a behavioral synthesis method for asynchronous circuits with bundled-data implementation. This paper extends a behavioral synthesis method for synchronous circuits so that an RTL model of bundled-data implementation is synthesized from a behavioral description specified by a restricted C language. Finally, this paper evaluates our method for several benchmarks through a tool implementation.
ISSN:1550-4808
2374-8567
DOI:10.1109/ACSD.2008.4574595