A novel method to analyze and design a NWL scheme DRAM

A novel method to analyze and design a NWL scheme DRAM

One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This...

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Hauptverfasser: Seokhan Park, Bonggu Sung, Hyuckchai Jung, Junhee Lim, Sangwoon Lee, Jooyoung Lee, Wonsuk Yang, Kyungseok Oh, Taeyoung Chung, Kinam Kim
Format: Tagungsbericht
Sprache:eng
Schlagworte:
Degradation
Doping
Failure analysis
Leakage current
Pattern matching
Probability distribution
Random access memory
Subthreshold current
Time measurement
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Zusammenfassung:One of the most important issues for DRAM development is the control of data retention time. A negatively-biased off-state level of the word line (NWL) was introduced to the memory cell design to improve cell transistor "on" current and to maintain "off current sufficiently low. This paper discusses a method to design cell transistor and NWL bias level to improve the data retention time in DRAM with NWL.
ISSN:1541-7026
1938-1891
DOI:10.1109/RELPHY.2008.4558996