Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process
Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among mul...
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| creator | Amusan, O.A. Massengill, L.W. Baze, M.P. Bhuva, B.L. Witulski, A.F. Black, J.D. Balasubramanian, A. Casey, M.C. Black, D.A. Ahlbin, J.R. Reed, R.A. McCurdy, M.W. |
| description | Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section. |
| doi_str_mv | 10.1109/RELPHY.2008.4558930 |
| format | Conference Proceeding |
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The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.</description><identifier>ISSN: 1541-7026</identifier><identifier>ISBN: 1424420490</identifier><identifier>ISBN: 9781424420490</identifier><identifier>EISSN: 1938-1891</identifier><identifier>EISBN: 9781424420506</identifier><identifier>EISBN: 1424420504</identifier><identifier>DOI: 10.1109/RELPHY.2008.4558930</identifier><identifier>LCCN: 82-640313</identifier><language>eng</language><publisher>IEEE</publisher><subject>charge sharing ; Circuit synthesis ; CMOS process ; Dual Interlocked Cell (DICE) latch ; guard-rings ; heavy-ion ; Isolation technology ; Latches ; MOS devices ; MOSFETs ; nodal separation ; Rails ; Redundancy ; single event circuit characterization ; Single event upset ; soft error cross-section ; Space charge</subject><ispartof>2008 IEEE International Reliability Physics Symposium, 2008, p.468-472</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4558930$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2058,27925,54920</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4558930$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Amusan, O.A.</creatorcontrib><creatorcontrib>Massengill, L.W.</creatorcontrib><creatorcontrib>Baze, M.P.</creatorcontrib><creatorcontrib>Bhuva, B.L.</creatorcontrib><creatorcontrib>Witulski, A.F.</creatorcontrib><creatorcontrib>Black, J.D.</creatorcontrib><creatorcontrib>Balasubramanian, A.</creatorcontrib><creatorcontrib>Casey, M.C.</creatorcontrib><creatorcontrib>Black, D.A.</creatorcontrib><creatorcontrib>Ahlbin, J.R.</creatorcontrib><creatorcontrib>Reed, R.A.</creatorcontrib><creatorcontrib>McCurdy, M.W.</creatorcontrib><title>Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process</title><title>2008 IEEE International Reliability Physics Symposium</title><addtitle>RELPHY</addtitle><description>Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.</description><subject>charge sharing</subject><subject>Circuit synthesis</subject><subject>CMOS process</subject><subject>Dual Interlocked Cell (DICE) latch</subject><subject>guard-rings</subject><subject>heavy-ion</subject><subject>Isolation technology</subject><subject>Latches</subject><subject>MOS devices</subject><subject>MOSFETs</subject><subject>nodal separation</subject><subject>Rails</subject><subject>Redundancy</subject><subject>single event circuit characterization</subject><subject>Single event upset</subject><subject>soft error cross-section</subject><subject>Space charge</subject><issn>1541-7026</issn><issn>1938-1891</issn><isbn>1424420490</isbn><isbn>9781424420490</isbn><isbn>9781424420506</isbn><isbn>1424420504</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2008</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotkMtOAjEYheuFxAF5AjZ9gcG_t2m7NATBBILxstANmbb_QBUGnA4mvr2TyOpLzndyFoeQEYMxY2DvnqeLp_n7mAOYsVTKWAEXZGi1YZJLyUFBcUkyZoXJmbHsivTPQlq47oSSLNfAix7JDM8LCYKJG9JP6ROAgzBFRj6WsY2bso2Hmrbot3X8PmGi1aGhKdabHVL8wbqlsQ4nj4H6bdlskKYOne5iWlILtN5Td9p90cly9UKPzcFjSrekV5W7hMMzB-TtYfo6meeL1exxcr_II9OqzUNwwXgeDFbeamUrLMFqKADRAbpQBebAoXYMg0IEYUNXsqiYqVBzLwZk9L8bEXF9bOK-bH7X57_EH0AoWm0</recordid><startdate>200804</startdate><enddate>200804</enddate><creator>Amusan, O.A.</creator><creator>Massengill, L.W.</creator><creator>Baze, M.P.</creator><creator>Bhuva, B.L.</creator><creator>Witulski, A.F.</creator><creator>Black, J.D.</creator><creator>Balasubramanian, A.</creator><creator>Casey, M.C.</creator><creator>Black, D.A.</creator><creator>Ahlbin, J.R.</creator><creator>Reed, R.A.</creator><creator>McCurdy, M.W.</creator><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope></search><sort><creationdate>200804</creationdate><title>Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process</title><author>Amusan, O.A. ; Massengill, L.W. ; Baze, M.P. ; Bhuva, B.L. ; Witulski, A.F. ; Black, J.D. ; Balasubramanian, A. ; Casey, M.C. ; Black, D.A. ; Ahlbin, J.R. ; Reed, R.A. ; McCurdy, M.W.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i175t-ddbd8c2d8efc9759fea097060eeb0ebdfd1b0be7b1ed5ee039d59f9e518fe72c3</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2008</creationdate><topic>charge sharing</topic><topic>Circuit synthesis</topic><topic>CMOS process</topic><topic>Dual Interlocked Cell (DICE) latch</topic><topic>guard-rings</topic><topic>heavy-ion</topic><topic>Isolation technology</topic><topic>Latches</topic><topic>MOS devices</topic><topic>MOSFETs</topic><topic>nodal separation</topic><topic>Rails</topic><topic>Redundancy</topic><topic>single event circuit characterization</topic><topic>Single event upset</topic><topic>soft error cross-section</topic><topic>Space charge</topic><toplevel>online_resources</toplevel><creatorcontrib>Amusan, O.A.</creatorcontrib><creatorcontrib>Massengill, L.W.</creatorcontrib><creatorcontrib>Baze, M.P.</creatorcontrib><creatorcontrib>Bhuva, B.L.</creatorcontrib><creatorcontrib>Witulski, A.F.</creatorcontrib><creatorcontrib>Black, J.D.</creatorcontrib><creatorcontrib>Balasubramanian, A.</creatorcontrib><creatorcontrib>Casey, M.C.</creatorcontrib><creatorcontrib>Black, D.A.</creatorcontrib><creatorcontrib>Ahlbin, J.R.</creatorcontrib><creatorcontrib>Reed, R.A.</creatorcontrib><creatorcontrib>McCurdy, M.W.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Amusan, O.A.</au><au>Massengill, L.W.</au><au>Baze, M.P.</au><au>Bhuva, B.L.</au><au>Witulski, A.F.</au><au>Black, J.D.</au><au>Balasubramanian, A.</au><au>Casey, M.C.</au><au>Black, D.A.</au><au>Ahlbin, J.R.</au><au>Reed, R.A.</au><au>McCurdy, M.W.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process</atitle><btitle>2008 IEEE International Reliability Physics Symposium</btitle><stitle>RELPHY</stitle><date>2008-04</date><risdate>2008</risdate><spage>468</spage><epage>472</epage><pages>468-472</pages><issn>1541-7026</issn><eissn>1938-1891</eissn><isbn>1424420490</isbn><isbn>9781424420490</isbn><eisbn>9781424420506</eisbn><eisbn>1424420504</eisbn><abstract>Mitigation techniques to reduce the increased SEU cross-section associated with charge sharing in a 90 nm DICE latch are proposed. The increased error cross-section is caused by heavy ion angular strikes depending on the directionality of the ion vector, thereby exacerbating charge sharing among multiple circuit nodes. The use of nodal separation as a mitigation technique shows an order of magnitude decrease on upset cross-section compared to a conventional layout and the use of guard-rings show no noticeable effect on upset cross-section.</abstract><pub>IEEE</pub><doi>10.1109/RELPHY.2008.4558930</doi><tpages>5</tpages></addata></record> |
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| identifier | ISSN: 1541-7026 |
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| issn | 1541-7026 1938-1891 |
| language | eng |
| recordid | cdi_ieee_primary_4558930 |
| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | charge sharing Circuit synthesis CMOS process Dual Interlocked Cell (DICE) latch guard-rings heavy-ion Isolation technology Latches MOS devices MOSFETs nodal separation Rails Redundancy single event circuit characterization Single event upset soft error cross-section Space charge |
| title | Mitigation techniques for single event induced charge sharing in a 90 nm bulk CMOS process |
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