A novel technique for mitigating neutron-induced multi -cell upset by means of back bias

We investigated the effect of back bias (V BB ) on neutron-induced multi-cell upset (MCU) in 65 nm low stand-by power SRAM. MCUs containing characteristic even number upsets were observed, and they were strongly related to the memory cell array layout. We concluded that most MCUs were induced by act...

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Hauptverfasser:	Nakauchi, T., Mikami, N., Oyama, A., Kobayashi, H., Usui, H., Kase, J.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	back bias CMOS technology ECC Equivalent circuits Error correction Error correction codes MCU multi-cell upset neutron Neutrons Nuclear power generation parasitic bipolar transistor Performance evaluation Random access memory SER soft error SRAM Testing Variable structure systems
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Zusammenfassung:	We investigated the effect of back bias (V BB ) on neutron-induced multi-cell upset (MCU) in 65 nm low stand-by power SRAM. MCUs containing characteristic even number upsets were observed, and they were strongly related to the memory cell array layout. We concluded that most MCUs were induced by activation of parasitic lateral npn-bipolar transistors. We also found that MCU could be drastically reduced by supplying V BB in the p-wells. The SER of MCU was reduced to 1/10 by supplying V BB = -2.0 V in the p-wells without any modification of error checking and correction (ECC) circuits.
ISSN:	1541-7026 1938-1891
DOI:	10.1109/RELPHY.2008.4558883