Flip chip back end design parameters to reduce bump electromigration

The advancement in flip chip technology has enabled us to meet the requirement of smaller die size along with the increased functionality. Due to this development in flip chip packaging technology along with higher current carrying requirement of solder bumps, electromigration has now become a reliability concern. In this paper, a commercially available finite element tool is adopted in order to study the distribution of current density in eutectic solder bump for variety of back end design parameters. Parameters such as passivation opening (PO) diameter, trace width, under bump metallurgy (UBM) thickness and UBM diameter were studied in detail. The results were evaluated for input currents of 0.1 A and 0.5 A. Based on the results, a guideline for solder bump configuration is proposed. In the metallization, the most important design attribute found is the Al trace width. In the solder bump, the most important parameters found are Al trace width and UBM thickness. In the metallization of the structures used in our study, current density varied from 5times10 5 A/cm 2 to 7times10 5 A/cm 2 and from 2.5times10 6 A/cm 2 to 3.5times10 6 A/cm 2 at 0.1 and 0.5 A per bump, respectively. In the solder of the structures used in our study, current density varied from 2.8times10 3 A/cm 2 to 4.2times10 4 A/cm 2 and from 1.4times10 4 and 2.1times10 5 A/cm 2 at 0.1 and 0.5 A per bump, respectively.