Efficient FPGA implementation of complex multipliers using the logarithmic number system

In many real-time DSP applications, high performance is a prime target. However, achieving this may be done at the expense of area, power dissipation and accuracy. Attempts have been made to use alternative number systems to optimize the realization of arithmetic blocks, maintaining high performance without incurring prohibitive area and power increases. This paper presents the FPGA implementation of complex multipliers based on the logarithmic number system. Synthesis results show that a design with a 10-stage pipeline can achieve a maximum clock rate of 224 MHz and 140 MHz for 16-bit and 32-bit designs, respectively. Both designs use the lowest amount of hardware in terms of gate equivalents as compared to a complex multiplier built with regular FPGA features. In particular, the proposed architecture uses 67% and 35% fewer gates to implement a 32-bit and 16-bit complex multiplier, respectively, when compared to a design realized with embedded multipliers. Simulation results based on selected test vectors show that the greatest relative error of the logarithmic-based 16-bit complex multiplier is 2.14%